This invention relates to the field of integrated circuit manufacturing. More particularly, the invention relates to shallow junction formation in integrated circuits.
One design goal for integrated circuits is to make the integrated circuit increasingly faster. One method of making an integrated circuit faster is to make it smaller. Thus, by creating increasingly smaller integrated circuits, not only can the design goal of faster integrated circuits be achieved, but the design goal of fitting more circuit elements within a given surface area can also be achieved.
Unfortunately, there are certain problems which arise as the geometries of integrated circuits are reduced. Some of these problems relate to conditions which tend to be inherent in the traditional designs of integrated circuits, but which conditions did not present a problem until the integrated circuits became smaller and faster.
For example, as integrated circuits become smaller in surface area, it is also generally necessary to make them shallower in depth. As the depth of the integrated circuits is decreased, some of the manufacturing processes that had traditionally been used to fabricate the integrated circuits became more difficult to control. For example, as junction depths for metal oxide semiconductor field effect transistors become shallower, it becomes harder to control the depth of the junction within a desired range, while achieving high dopant concentrations simultaneously.
Other problems also become more of an issue. For example, the junction capacitance to the substrate tends to create more problems as the integrated circuit operates at higher speeds and increased dopant activations. The junction capacitance tends to slow the integrated circuit because of the time delay that tends to be required to charge and discharge the effective capacitor that is formed due to coupling of the junction to the substrate.
What is needed, therefore, is a method for improving the switching speed of an integrated circuit by forming a controlled shallow junction with reduced junction capacitance.
The above and other needs are met by a method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within a first depth zone through the second portions of the substrate. The first depth zone extends from a first depth to a second depth, and the first depth is shallower than the second depth. The substrate is annealed for a first time to form a noncontiguous high quality buried insulating layer substantially within the first depth zone in the second portions of the substrate.
After undergoing a generally standard CMOS process flow, the substrate is masked with a second mask to selectively cover third portions of the substrate and selectively expose fourth portions of the substrate. The fourth portions of the substrate at least partially overlap the second portions of the substrate. A second dopant is implanted substantially within a second depth zone through the fourth portions of the substrate. The second depth zone extends from an upper surface of the substrate to the first depth.
The substrate is annealed for a second time to activate the shallow junctions formed substantially within the second depth zone in the fourth portions of the substrate. The shallow junctions have a depth that is substantially limited by the noncontiguous buried insulating layer that starts at the first depth.
By forming the noncontiguous buried insulating layer in the manner as described above, the shallow junctions are able to be formed to a fairly precisely determined and relatively shallow depth without spiking and shorting of the junctions. Thus, the speed of the integrated circuit incorporating the shallow junctions is enhanced. Further, by having the noncontiguous buried insulating layer under the shallow junctions, the substrate capacitance problems described above are substantially reduced. In addition, the noncontiguous buried insulating layer preferably does not substantially underlie a channel portion of the integrated circuit. Therefore, the substrate is preferably not electrically insulated from the channel portion of the integrated circuit, and majority carriers can be collected from the substrate when the channel portion of the integrated circuit is activated.
In various preferred embodiments of the method, the first dopant is one or more of oxygen, nitrogen, and argon. The second dopant is preferably one or more of indium, boron, phosphorous, and arsenic. The mask may be either a photoresist mask having properties that are compatible with the processing and functions as described herein, or a hard mask of a material such as silicon nitride or polysilicon, or other materials having properties that are compatible with the processing and functions as described herein.
The step of annealing the substrate for a first time is preferably conducted at a temperature of between about one thousand centigrade and about eleven hundred and fifty centigrade, and the first time is preferably between about one hour and about fifteen hours. The first depth is preferably, for example, about sixty nanometers and the second depth is about seventy nanometers. This is specific to technology generation and device design and must be considered guidelines. The fourth portions of the substrate are preferably wholly disposed within the second portions of the substrate.
In another aspect the invention provides for an integrated circuit having shallow junctions formed according to the method as described above.